New Methodologies for Advanced Packaging Design
Rita Glover, EDA Today, L.C.
April 2001
The convergence of communications, computing, and multimedia
is bringing unprecedented challenges to design technologies. To meet
the demands for increased performance, lower cost, and faster time to
market, the design community now requires a similar convergence of tools and
methodologies.
Today, the ability to concurrently design a chip, its
package, and the surrounding system becomes a huge advantage. The
influence of the package on system performance must be understood and
analyzed early in the design cycle. Concurrent package design is
becoming an important bridge between the design of high-performance chips
and the printed circuit assembly on which the finished chip will operate.
As the push toward systems-on-chips (SOCs) and deep
submicron continues, the industry trend is toward more complex, high-density
packaging. System-level packages (SLPs) are gaining acceptance as a
viable alternative to SOCs as the industry begins to face the challenge of
integrating multiple technologies on a single chip. With the SLP
approach, one or more ICs -- which may contain discrete and embedded
components -- can be integrated in a single high-performance, compact
package. But this higher performance is causing tremendous problems
with signal integrity -- simultaneous switching noise problems, crosstalk
problems, and resonance problems. So we're critically constraining the
chip, and the layout of those signals is now much more important.
Thus, the ability to do concurrent IC, package, and system
design using a single interactive database means that design teams can
perform high-speed interconnect analysis -- both physical and electrical --
and make optimization trade-offs among all these levels. The design
methodology of the future must support collaborative design in order to
remove the barriers between chip vendors, package suppliers, and the
customer.
A new methodology for concurrent design of an SLP is shown
in Figure 1. The left column looks at the requirements from the
perspective of the IC designer. IC designers need the target die size,
the I/O requirements, the I/O layout, and the I/O buffer models in order to
perform verification on the chip. But where do they get that
information?
Figure 1: Interactions required for concurrent
design of the chip, the package, and the printed circuit board. A true
chip/package/PCB co-design solution can be realized when tools share a
common database and common analysis engines.
It really needs to come through various interactions with
the package designer. For instance, the die size must be based on
physical feasibility studies. The I/O requirements should be driven by
electrical feasibility studies that would be done for a package in order to
understand what the performance matrix will look like. The I/O layout
must be driven by what the package will look like, with an I/O template that
is known to be routable and meet the performance matrix. Out of these
the package designer will extract the package performance analysis.
Once a package has been built up through co-design with the IC, a model of
the final package can be created.
At the same time, the PCB designers are trying to determine
the I/O buffer limits and interconnect feasibility. In the PCB world,
designers are having problems being able to escape route the huge BGA
components that are coming onto the scene now, and they need to understand
the interconnect feasibility. They also need to be able to determine
the timing coupling margins, which are based on the placement of the printed
circuit board. The team needs to be able to feed that information back
to the package and IC designers so that they'll know what their timing and
coupling budgets are. The same goes for signal performance prediction.
How much can they predict, and at what level of accuracy?
Why is it important to design the package along with the IC
and the board? What are the advantages of doing it together? Why
can't you just use an off-the-shelf package? For high-performance
devices, once these critical nets get onto the package, all kinds of nasty
things can happen. Typically, there are crosstalk problems, reflection
issues, impedance values that need to be maintained, differential pairs that
have to be accounted for, and power and ground planes that can either be
implemented or not within the package depending on the performance.
Another issue is time to market. If the IC design team
has no idea of what is going on in the package or at the board level, the
resulting device often fails. It can quite easily violate the noise
budget without the knowledge of the designer, requiring a re-spin of the
package. This is certainly a cost issue, but it's really more of a
time-to-market issue, because it could take as long as twelve weeks to
re-spin one of these packages. Packages have a significant design
cycle--much longer than it takes to do a chip or a new PCB.
PCB designers are now saying that they need drive the
package design just as much as the IC designers do, because PCBs now are
becoming so complicated, expensive, and difficult to route. Today's
system design teams need that capability where customers, depending on their
requirements, can either drive the design from the PCB level up into the
chip, or from the chip down into the PCB.
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