Rita Glover, EDA Today, L.C.
January 2002
The new silicon virtual prototyping sector of the electronic design
automation marketplace has aroused a great deal of interest in recent weeks.
Cadence Design Systems recently announced the acquisition of the top virtual
prototyping tool vendor, Silicon Perspective Corp. Rumors have it that
the acquisition price was between $200–300 million USD. For a company
whose revenues were only around $10 million, that’s a whopping 20-30X
multiple. So what’s all the excitement about?
Gartner Dataquest forecasts that revenues for the silicon virtual
prototyping sector will reach a compound annual growth rate of 60% over the
next five years. This growth is being driven by the fact that
designing and implementing multi-million-gate systems on chips (SoCs) has
become a very complex, expensive, and risky business.
To assure that results from a design’s physical layout match those
reported by logic synthesis, logic designers now need a full-chip view so
that they can consider the physical details of the chip’s wiring, floorplan,
and timing during the earliest phases of design. Achieving this
convergence between the front-end estimation and the actual layout is a key
strategy for shortening the design time with today’s deep-submicron ASICs
and SoCs.
Silicon virtual prototyping tools have evolved as a solution to this
problem by estimating silicon-level chip performance during the early steps
of logic design. They work by synthesizing a Register-Transfer Level
(RTL) design description into a virtual silicon implementation and then
reporting the estimated silicon performance to the logic designer.
“Many of the problems that people have with timing convergence and design
closure stem from the fact that their architectures had hidden flaws that
they couldn’t understand until they got all the way through implementation,”
said Mark Miller, vice president of marketing at Tera Systems (Campbell,
California). “The need we’re trying to serve is to let them see the
overall critical timing paths, the timing budget, the area implications, and
the approximate floorplan that would be best used to implement the design
that they’ve specified in RTL.”
Tera Systems’ toolsuite, TeraForm, offers front-end RTL design planning,
analysis, and prototyping tools for complex SoC designs. Tera Systems
has been working with NEC Electronics on library, tool, and methodology
refinements to deliver early, rapid feedback on design quality to designers
through creation of RTL-based virtual prototypes. NEC will certify
TeraForm and the necessary libraries for customer use within NEC’s design
flows for ASICs and SoCs. Also, LSI Logic just signed a multi-year
agreement to outfit its design centers with the TeraForm technology.
Other major ASIC vendors such as Fujitsu and IBM Microelectronics are
introducing TeraForm into their ASIC design flows.
The underlying problem is that the gate-level signoff methodology is
simply failing at this point. There are now many horror stories of
designs that used gate-level signoff that did not meet timing goals, did not
tape out on time, and did not meet the customer’s performance requirements.
The new trend is toward the practice of RTL handoff, where the end designers
hand over the RTL design to their implementation partner — the ASIC vendor —
rather than trying to hand off a timing-qualified, gate-level netlist.
To achieve results with this methodology, both sides of the relationship
need to have a good understanding of the RTL, and that’s where the virtual
silicon prototyping tools come in.
So who will do the synthesis step now, the customer or the ASIC vendor?
Miller says, “If you’re going to try to take front-end designers at systems
companies who don’t know much about physical design and try to turn them
into back-end experts, it’s going to be a difficult challenge.” The
worldwide trend is toward the handoff of RTL code from the customer to a
team of physical design experts inside the ASIC vendor. These physical
design experts then perform the implementation step using some of the recent
integrated synthesis, placement, and routing tools such as Cadence PKS,
Synopsys Physical Compiler, or Avant! Astro.
Figure 1. The
conventional design flow has been changed by deep submicron processes and
the integration of synthesis, place and route. The new design flow
requires earlier signoff, so there’s no iteration to be done between the
front and back ends. Thus, RTL virtual prototyping tools are
required to accurately estimate final chip performance during front-end
design.
The gate-level signoff methodology has essentially been invalidated by
both the new generation of tools that combine the synthesis, placement, and
routing steps, as well as the latest generation of semiconductor
manufacturing technology (0.13 micron processes and below). Because
the next-generation technology has integrated synthesis with place and
route, you can no longer hand off a gate-level netlist, because the final
implementation tool needs to start at a higher level of abstraction.
With this new flow, the iteration between front and back ends has been
eliminated. Moving forward, ASIC and SoC designers will need to employ
design planning tools at the earliest stages of logic design to rapidly
create accurate chip architectures.
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