Design Libraries Signal Shift to New IC Processes
Rita Glover, EDA Today, L.C.
February 2003
Signaling the beginning of a shift to very dense IC
geometries, alliances are being formed to deliver design libraries for
advanced semiconductor technologies at pure-play IC foundries. While
widespread adoption of 90-nanometer processes is not anticipated until 2004,
design work using these processes is now in progress by some early adopters,
and those chips will start to appear in the first half of 2003.
Taiwan Semiconductor Manufacturing Company, for example, has
new classes of libraries for three generations of process technology -- 0.15
micron, 0.13 micron, and 90 nanometer -- and is widening the development,
distribution, and support channel for these libraries to multiple
third-party library developers and EDA partners. This constitutes a
new business model for the industry and will improve the toolsets and
services available for designers using advanced processes.
TSMC has new licensing deals with library vendors Artisan
Components and Virage Logic, as well as EDA vendors Cadence, Synopsys, and
Magma. IBM announced an alliance with Chartered Semiconductor to give
customers an additional source of manufacturing capacity for its advanced
processes, and this too will involve a broadening of library support.
Collaboration with EDA tool developers helps create an
integrated design chain that provides better technical services to
designers. "There's a great deal of synergy between the process, the
library, and the EDA tools," explained Genda Hu, vice president of marketing
at TSMC. "The technology libraries themselves are developed using EDA
tools. If the tools used to develop the libraries are aligned with the
tools used in the foundry's reference flow, it increases the probability
that the library will work in the foundry's processes."
The timing is coming together all at once now, because EDA
and library vendors have had the foundries' early-version design rules for
at least nine months, and they are at the point where they are validating IP
in silicon and verifying reference flows at the same time.
The classic development process for embedded systems splits
into two design flows after the specification stage. The software flow
involves a high-level programming language, and serial execution. The
hardware flow requires a high-level HDL, parallel execution, and an
understanding of the structures involved. Analog is treated as an
afterthought, and often must be performed by an expert.
TSMC's structured process for helping
customers evaluate technology libraries. Source: Taiwan
Semiconductor Manufacturing Company
Foundries, library vendors, and EDA vendors operate as part
of a design supply chain or "ecosystem." Although integrated device
manufacturers (IDMs) and ASIC vendors have disaggregated, chip designers
still need the same things as always, and today these things are supplied by
different types of players in the design chain.
Formerly, an ASIC vendor provided tools, libraries, product
engineering, and foundry services to the customer. But customers
objected to the fact that once they were locked into an ASIC vendor's
technology, it was difficult to switch foundries and achieve the cost
benefits that can accrue as a product matures. The ASIC vendors
pocketed that money, and that's why they were so profitable.
With the advent of pure-play foundries in the mid-90s, the
economics changed. The price of a wafer dropped from $15,000 to
$2,000, but the users of a pure-play foundry had to fend for themselves with
respect to the libraries, tools, and product engineering.
Moore's Law has three dependencies, any of which can stop
its advance: fab equipment, materials science, and lithography.
But designers don't want to worry about these issues. The library
vendor's job is to insulate the designer from Moore's Law, and reduce the
risks in foundry selection.
Library components bridge the gap from design to
manufacturing, and each one needs to be as accurate a characterization of
the silicon as possible. A library vendor is expected to provide
accurate "views" for EDA tools that can be validated by the EDA vendor.
And conversely, the library vendor verifies that EDA tools work as reported
in silicon. So it's a symbiotic relationship.
The challenge is to get everybody to the finish line at
once. EDA tool developers are always trying to deliver tools to serve
a new process node in advance of customer adoption of that process.
And library vendors would like the EDA views in their libraries to be as
concurrent as they can be with the process release.
"EDA vendors look to the library developers to provide views
for their tools as soon as the tools are available," said James Hogan,
senior vice president of business development at Artisan. "An EDA
vendor can release a new tool, but it will only get used when there's IP.
So EDA vendors have realized they need to be active in working with library
suppliers."
Artisan sometimes gets third parties to invest up front in
the creation of new libraries. "We only invest in developing a new
library when the market asks us to — when there's a customer," said Hogan.
"As a result, our investment may be a bit behind what an EDA vendor might
want, or what a foundry would want. To address this, they themselves
sometimes invest in a library in advance of the demand if they have
something different, or if they need to launch a little faster."
In the future, instead of building their own fabs, IDMs will
increasingly look to manufacture their chips at pure-play foundries.
For cost reasons, they will not want to be tied to any specific foundry, so
they will start to contract with library developers to create their own
proprietary libraries that are portable among multiple foundries.
So it always comes back to EDA tools and expertise.
Without leadership capabilities for designing these high-complexity chips,
the value of leading-edge fabs and process technologies is limited.
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